The voltage spikes which appear as noise on the ground lines and power supply lines of integrated circuit devices have increased both in prevalence and relative magnitude with the evolution toward smaller integrated circuit dimensions. Investigations have established that the resistance and inductance of the interconnect lines within the integrated circuit chip have become major sources of transient noise voltages. Rapid changes of current to and from the power supply and ground pads contribute significantly to the levels of noise on such corresponding lines throughout the chip. Concurrently, decreases in integrated circuit dimensions constrain designers from materially reducing the power supply and ground line impedance levels by expanding line widths. Attempts to eliminate or suppress noise sources are further complicated by the increases in the integrated circuit device switching speeds and their associated di/dt effects.
Integrated circuit power supply and ground line noise signals attributable to resistance and di/dt effects appear most often when input/output (I/O) buffers are used to switch capacitive loads. The significance of this noise source is expected to increase with the use of more CMOS type integrated circuits, in that CMOS integrated circuit loads are predominantly capacitive.
The above-identified copending applications relate to inventions which suppress switching noise. U.S. Patent application Ser. No. 07/072,831 utilizes parallel configured sets of inverter transistors which are enabled in timed succession to increase with time the effective current passed to the pad. The other referenced copending patent application, identified as Ser. No. 07/233,506, involves a pad driver circuit which incrementally increases the signal used to drive the output pad voltage. The objectives of the two referenced applications are in distinct contrast to the present invention, particularly to the extent that the present invention is responsive in a feedback sense to the capacitive magnitude of the load.
A number of circuits and techniques to eliminate or suppress power supply and ground line noise have been proposed in prior references. For example, U.S. Pat. No. 4,129,792 defines a circuit in which the output drive current is contributed by two or more switching devices enabled in timed succession depending on the switching speed of cascaded transistor stages. U.S. Pat. No. 4,638,187 teaches another arrangement of parallel connected transistor stages, successively enabled in time to minimize current spike effects. A further arrangement is taught in U.S. Pat. No. 4,727,266, wherein the output current is limited merely by undersizing the dimensions of the transistors furnishing current to the control electrode of the output inverter stage. And lastly, application of a concept similar to one set forth in U.S. Pat. application Ser. No. 07/072,831 appears in the article authored by Leung, entitled "Controlled Slew Rate Output Buffer", and which was published in the proceedings of the IEEE 1988 Custom Integrated Circuit Conference on pages 5.5.1-5.5.4.
Although the techniques disclosed in the various references eliminate some power supply line and ground line switching noise problems typical of advanced integrated circuit products, there remains a need for a circuit which adjusts the rate of change of the output buffer current in relation to the magnitude of the capacitive load on the output pad. Preferably, such rate of change compensation would, in response to feedback signals, limit rapid current changes and thereby constrain associated power supply and ground line di/dt noise levels.